Basic Operational Timing; Access To On-Chip Memory (Ram, Rom) - Renesas H8 Series Hardware Manual

Section 2 CPU
15
Legend:
op:
2.6

Basic Operational Timing

CPU operation is synchronized by a system clock (φ) or a subclock (φ
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ
the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle
differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1

Access to On-Chip Memory (RAM, ROM)

Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
φ or φ
SUB
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
Rev. 6.00 Sep 12, 2006 page 44 of 526
REJ09B0326-0600
Operation field
Figure 2.10 Block Data Transfer Instruction Code
Figure 2.11 On-Chip Memory Access Cycle
8 7
op
op
Bus cycle
T state T
1 2
Address
Read data
Write data
0
). For details on these
SUB
state
to
SUB