Basic Timing; Figure 6.20 Dram Basic Access Timing (Rast = 0, Cast = 0) - Renesas H8S/2368 Series Hardware Manual

6.6.5

Basic Timing

Figure 6.20 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one T
output cycle) state, and the T
Address bus
Read
Data bus
Write
Data bus
Note: n = 2, 3

Figure 6.20 DRAM Basic Access Timing (RAST = 0, CAST = 0)

When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When
connecting DRAM provided with an EDO page mode, the OE signal should be connected to the
(OE ) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM
space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is output
from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space,
the signal is output only from the RD pin.
and two T
c1 c2
T
p
Row address
( )
,
( )
( )
( )
( )
(precharge cycle) state, one T
p
(column address output cycle) states.
T T
r
High
High
(row address
r
T
c1 c2
Column address
Rev. 2.00, 05/03, page 155 of 820