Section 7 Bus Controller; Basic Timing; On-Chip Memory Access Timing (Rom, Ram); Figure 7.1 On-Chip Memory Access Cycle - Renesas H8S Series Hardware Manual

The H8S/2600 CPU is driven by a system clock, denoted by the symbol ø.
The bus controller controls a memory cycle and a bus cycle. Different methods are used to access
on-chip memory and on-chip support modules. The bus controller also has a bus arbitration
function, and controls the operation of the internal bus masters: the CPU and data transfer
controller (DTC).
Note: The DTC, MMT, and POE are not supported in H8S/2614 and H8S/2616.
7.1

Basic Timing

The period from one rising edge of ø to the next is referred to as a "state". The memory cycle or
bus cycle consists of one, two, three, or four states. Different methods are used to access on-chip
memory, on-chip support modules, and the external address space.
7.1.1

On-Chip Memory Access Timing (ROM, RAM)

On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 7.1 shows the on-chip memory access cycle.
φ
Internal address bus
Read
access
Write
access

Section 7 Bus Controller

Internal read signal
Internal data bus
Internal write signal
Internal data bus

Figure 7.1 On-Chip Memory Access Cycle

Section 7 Bus Controller
Bus cycle
T
1
Address
Read data
Write data
Rev. 6.00 Mar 15, 2006 page 97 of 570
REJ09B0211-0600