Basic Timing; Overview; On-Chip Memory (Rom, Ram) - Renesas H8S Series Hardware Manual

(3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In
hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset,
but as long as a specified voltage is supplied, on-chip RAM contents are retained.
2.9

Basic Timing

2.9.1

Overview

The CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is
referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to
access on-chip memory, on-chip supporting modules, and the external address space.
2.9.2

On-Chip Memory (ROM, RAM)

On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction.
Figure 2-14 shows the on-chip memory access cycle. Figure 2-15 shows the pin states.
ø
Internal address bus
Read
access
Write
access
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Figure 2-14 On-Chip Memory Access Cycle
Bus cycle
T
1
Address
Read data
Write data
Rev.6.00 Oct.28.2004 page 51 of 1016
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