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Operational Timing; Bus Timing - Renesas F-ZTAT H8 Series Hardware Manual

16-bit single-chip microcomputer
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Section 22 Electrical Characteristics
22.3

Operational Timing

This section shows timing diagrams.
22.3.1

Bus Timing

Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 22.7 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 22.8 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 22.9 shows the timing of the external three-state access cycle with one wait state
inserted.
Rev. 7.00 Sep 21, 2005 page 712 of 878
REJ09B0259-0700

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