Bus Hold Timing - Renesas PFESiP/V850EP1 User Manual

(3) Bus hold timing

Parameter
HLDRQZ setup time (to BUSCLK ↑ )
HLDRQZ hold time (from BUSCLK ↑ )
Delay time from BUSCLK ↑ to HLDAKZ
HLDRQZ high-level width
HLDAKZ low-level width
Delay time from BUSCLK ↑ to bus float
Delay time from BUSCLK ↑ to bus output
Delay time from HLDRQZ ↓ to HLDAKZ ↓
Delay time from HLDRQZ ↑ to HLDAKZ ↑
Remark t : BUSCLK cycle
BCLK
30
CHAPTER 1 PRODUCT SPECIFCATIONS
Table 1-14. Bus Hold Timing
Symbol MIN.
t 3.8
SHRK
t 2.0
HKHR
t 1.5
DKHA
t 5.8 + t
WHQH
− 9.5 + t
t
WHAL
t 1.5
DKCF
t 1.5
DHAC
t 1.5 × t
DHQHA1
0.5 × t
t
DHQHA2
User's Manual A19069EJ2V0UM
MAX.
BCLK
BCLK
BCLK
3 × t
BCLK BCLK
Unit
−
ns
−
ns
11.0 ns
− ns
−
ns
−
ns
13.0 ns
− ns
+ 3.8
ns