Configuration Of The Can Module System Clock; Can Bus Timing Control - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

Configuration of the CAN Module System Clock

The M16C/6N5 group has a CAN module system clock select circuit.
Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the
BRP bit of the C0CONR register.
For the CCLKR register, refer to "Clock Generation Circuit".
Figure 1.19.20 shows a block diagram of the clock generation circuit of the CAN module system.
X
IN
Divider
Value: 1, 2, 4, 8, 16
CCLKR register
f : CAN module system clock
CAN
P: The value written in the BRP bit of the C0CONR register. P = 0 to 15
f : CAN communication clock f
CANCLK
Figure 1.19.20 Block Diagram of CAN Module System Clock Generation Circuit

CAN Bus Timing Control

Bit Timing Configuration
The bit time consists of the following four segments:
• Synchronization segment (SS)
This serves for monitoring a falling edge for synchronization.
• Propagation time segment (PTS)
This segment absorbs physical delay on the CAN network which amounts to double the total sum of
delay on the CAN bus, the input comparator delay, and the output driver delay.
• Phase buffer segment 1 (PBS1)
This serves for compensating the phase error. When the falling edge of the bit falls later than expected,
the segment can become longer by the maximum of the value defined in SJW.
• Phase buffer segment 2 (PBS2)
This segment has the same function as the phase buffer segment 1. When the falling edge of the bit
falls earlier than expected, the segment can become shorter by the maximum of the value defined in
SJW.
Figure 1.19.21 shows the bit timing.
The range of each segment: Bit time = 8 to 25Tq
Figure 1.19.21 Bit Timing
Rev.1.00 2003.05.30 page 218
Divide-by-1 of X (undivided)
IN
Divide-by-2 of X
IN
Divide-by-4 of X
IN
Divide-by-8 of X
IN
Divide-by-16 of X
IN
= f
CANCLK CAN
Bit time
SS PTS PBS1
SS = 1Tq
PTS = 1Tq to 8Tq
PBS1 = 2Tq to 8Tq
PBS2 = 2Tq to 8Tq
SJW = 1Tq to 4Tq
Prescaler
f
CAN
1/2
Division by (P + 1)
CAN module
/2(P + 1)
PBS2
SJW SJW
Sampling point
Configuration of PBS1 and PBS2: PBS1 ≥ PBS2
CAN Module
Prescaler
f
CANCLK
for baud rate
PBS1 ≥ SJW
PBS2 ≥ 2 when SJW = 1
PBS2 ≥ SJW when 2 ≤ SJW ≤ 4