Basic Timing; Figure 6.9 Bus Timing For 8-Bit, 2-State Access Space - Renesas H8S/2368 Series Hardware Manual

6.5.3

Basic Timing

8-Bit, 2-State Access Space: Figure 6.9 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states can be inserted.
Address bus
D15 to D8
Read
D7 to D0
Write
D15 to D8
D7 to D0
Notes: 1. n = 0 to 7
2. When RDNn = 0

Figure 6.9 Bus Timing for 8-Bit, 2-State Access Space

Rev. 2.00, 05/03, page 140 of 820
Bus cycle
T T
1 2
High
Valid
High impedance
Valid
Invalid