Register Settings - Renesas F-ZTAT H8 Series Hardware Manual

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Section 14 Smart Card Interface

designated interval, the receiving device returns the signal line to the high-impedance state.

The signal line is pulled back up to the high level through the pull-up resistor.

5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data.

If it receives an error signal, it returns to step 2 and transmits the same data again.

Register Settings

Table 14.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or

1 should always be set to the indicated value. The settings of the other bits will be described in this

Table 14.3 Register Settings in Smart Card Interface

Legend: — Unused bit.

Notes: 1. Lower 16 bits of the address.

2. When the GM of the SMR is set at 0, be sure the CKE1 bit is 0.

Serial Mode Register (SMR) Settings: In regular smart card interface mode, set the GM bit at 0.

In regular smart card mode, clear the GM bit to 0. In GSM mode, set the GM bit to 1. Clear the

O/E bit to 0 if the smart card uses the direct convention. Set the O/E bit to 1 if the smart card uses

the inverse convention. Bits CKS1 and CKS0 select the clock source of the built-in baud rate

generator. See section 14.3.5, Clock.

Bit Rate Register (BRR) Settings: This register sets the bit rate. Equations for calculating the

setting are given in section 14.3.5, Clock.

Serial Control Register (SCR): The TIE, RIE, TE, and RE bits have their normal serial

communication functions. For details, see section 13, Serial Communication Interface. The CKE1

and CKE0 bits select clock output. When the GM bit of the SMR is cleared to 0, to disable clock

output, clear this bit to 00. To enable clock output, set this bit to 01. When the GM bit of the SMR

is set to 1, clock output is enabled. Clock output is fixed at high or low.

Rev. 3.00 Mar 21, 2006 page 506 of 814

REJ09B0302-0300