Dram Interface; Overview; Setting Dram Space; Address Multiplexing - Renesas H8S Series Hardware Manual

6.5

DRAM Interface

6.5.1

Overview

When the H8S/2357 Group is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and
DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the H8S/2357 Group. A
DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also
possible, using fast page mode.
6.5.2

Setting DRAM Space

Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH. The relation between the
settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6-5. Possible DRAM space settings are: one area
(area 2), two areas (areas 2 and 3), and four areas (areas 2 to 5).
Table 6-5 Settings of Bits RMTS2 to RMTS0 and Corresponding DRAM Spaces
RMTS2
0
6.5.3

Address Multiplexing

With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of
the row address is selected with bits MXC1 and MXC0 in MCR. Table 6-6 shows the relation between the settings of
MXC1 and MXC0 and the shift size.
Table 6-6 Address Multiplexing Settings by Bits MXC1 and MXC0
MXC1 MXC0 Size
Row 0
address
1
Column —
address
6.5.4

Data Bus

If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit
DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, × 16-bit
configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D
lower halves of the data bus, D
Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data Size and Data
Alignment.
Rev.6.00 Oct.28.2004 page 138 of 1016
REJ09B0138-0600H
RMTS1 RMTS0
0 1
1 0
1
MCR
Shift
A
23
0 8 bits A
23
1 9 bits A
23
0 10 bits A
23
1 Setting —
prohibited
— — A
23
to D , are enabled.
15 0
Area 5 Area 4
Normal space
Normal space
DRAM space
Address Pins
to A A A A A
13 12 11 10 9
to A A A A A
13 20 19 18 17
to A A A A A
13 12 20 19 18
to A A A A A
13 12 11 20 19
— — — — — — — — — — — — —
to A A A A A
13 12 11 10 9
to D , is enabled, while in 16-bit DRAM space both the upper and
15 8
Area 3 Area 2
DRAM space
DRAM space
A A A A A A
8 7 6 5 4 3
A A A A A A
16 15 14 13 12 11
A A A A A A
17 16 15 14 13 12
A A A A A A
18 17 16 15 14 13
A A A A A A
8 7 6 5 4 3
A A A
2 1 0
A A A
10 9 8
A A A
11 10 9
A A A
12 11 10
A A A
2 1 0