Exception Vector Address At A Reset In Each Boot Mode; Boot Mode 0 - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
3.4

Exception Vector Address at a Reset in Each Boot Mode

In this LSI, the exception vector address at a reset differs depending on the boot mode.
In this LSI, the exception vector at a reset starts from H'0000_0000 (low vector) in boot mode 0 and from H'FFFF_0000
(high vector) in boot modes 1 to 3.
In this LSI, an on-chip ROM is allocated in area H'FFFF_0000 to H'FFFF_FFFF. The on-chip ROM has a boot program
which executes processing corresponding to the boot mode set by the MD_BOOT1 and MD_BOOT0 external pins.
Table 3.3 lists the exception vector address at a reset for each boot mode.
Table 3.3 Exception Vector Address at a Reset in Each Boot Mode
Boot Mode

Boot Mode 0

(CS0-space 16-bit booting)
Boot Mode 1
(Serial flash booting)
Boot Mode 2
(eSD booting)
Boot Mode 3
(eMMC booting)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Exception Vector Address at a Rest
H'0000 0000 (low vector)
H'FFFF 0000 (high vector)
H'FFFF 0000 (high vector)
H'FFFF 0000 (high vector)
Memory Allocated at the Exception
Vector Address
Memory connected to the CS0 space
On-chip ROM (boot program)
On-chip ROM (boot program)
On-chip ROM (boot program)
3. Boot Mode
3-3