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18.4.8
Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 18.21 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
SCL or
SDA input
signal
Sampling
clock
18.4.9
Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in ICRES or
clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 18.3.7, I
Control Initialization Register (ICRES).
(1)
Scope of Initialization
The initialization executed by this function covers the following items:
• ICDRE and ICDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
Sampling clock
C
D
Q
Latch
System clock
cycle
Figure 18.21 Block Diagram of Noise Canceler
C
D
Q
Match
detector
Latch
Rev. 1.00 Apr. 28, 2008 Page 579 of 994
2
Section 18 I
C Bus Interface (IIC)
Internal
SCL or
SDA
signal
2
C Bus
REJ09B0452-0100
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