Iric Setting Timing And Scl Control - Renesas Hitachi H8S/2194 Series Hardware Manual

25.3.6

IRIC Setting Timing and SCL Control

The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR,
the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1,
SCL is automatically held low after one frame has been transferred; this timing is synchronized
with the internal clock. Figure 25.12 shows the IRIC set timing and SCL control.
Rev. 2.0, 11/00, page 558 of 1037