Iric Setting Timing And Scl Control; Figure 13.25 Iric Setting Timing And Scl Control (1) - Renesas H8S/2111B Hardware Manual

13.4.7

IRIC Setting Timing and SCL Control

The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred in synchronization with the internal
clock. Figures 13.25 to 13.27 show the IRIC set timing and SCL control.
When WAIT = 0, and FS = 0 or FSX = 0 (I
SCL
7
SDA
7
IRIC
User processing
SCL
7
SDA
7
IRIC
User processing

Figure 13.25 IRIC Setting Timing and SCL Control (1)

2
C bus format, no wait)
8 9
8 A
Clear IRIC
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
8 9
8 A
Clear IRIC
(b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception.
1 2
1 2
Write to ICDR (transmit)
or read from ICDR (receive)
Rev. 1.00, 05/04, page 331 of 544
3
3
1
1
Clear IRIC