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2.16 Power Control Usage
2.16.1 Overview of the power control usage
'Power Control' refers to the reduction of CPU power consumption by stopping the CPU and oscillators,
or decreasing the operation clock. The following is a description of the three available power control
modes:
(1) Modes
Power control is available in three modes.
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(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK
selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the BCLK selected. Each peripheral function operates
according to its assigned clock.
• Low-speed mode
f
becomes the BCLK. The CPU operates according to the fc clock. The f
C
secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fc
clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate
are those with the sub-clock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 2.16.1 is the state transition diagram of the above modes.
(2) Switching the driving capacity of the oscillation circuit
Both the main clock and the secondary clock have the ability to switch the driving capacity.
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
page 274 of 354
2. Power Control
clock is supplied by the
C
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