I 2 C0 Clock Control Register (S20 Register); Bits 0 To 4: Scl Frequency Control Bits (Ccr0-Ccr4); Bit 5: Scl Mode Specification Bit (Fast Mode); Bit 6: Ack Bit (Ack Bit) - Renesas M16C/29 Series Hardware Manual

M16C/29 Group
2
16.3 I C0 Clock Control Register (S20 register)
2
The I C0 clock control register (address 02E4
frequency.
16.3.1 Bits 0 to 4: S
These bits control the S
SCL frequency.
16.3.2 Bit 5: S
This bit specifies S
set to "1" , high-speed clock mode is selected. When connecting to the bus with high-speed mode I
standard (maximum 400 kbits/s), set 4 MHz or more to the I

16.3.3 Bit 6: ACK bit (ACK BIT)

This bit sets the S
mode is selected and the S
return mode is selected. The S
when the address data is received at the ACK BIT=0 and the slave address matches with the address data,
the S is automatically set to "L" (ACK is returned). If the slave address does not match with the address
DA
data, the S is automatically set to "H" (ACK is not returned).
DA
Note 1. ACK clock: Clock for acknowledgment

16.3.4 Bit 7: ACK clock bit (ACK)

This bit specifies mode of acknowledgment for responses to transfer data. When this bit is set to "0", no
ACK clock mode is selected. In this case, the ACK clock is not generated after the data transmit. When
the bit is set to "1", ACK clock mode is selected and the master generates an ACK clock at the completion
of each 1-byte data transfer. The device for transmitting the address data and the control data releases the
S at the ACK clock generation (set the S
DA
device.
Note . Do not rewrite the data into the I
the transfer. If data is written during the transfer, the I
not be transferred normally.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
frequency control bits (CCR0–CCR4)
CL
frequency. See Table 16.3 Set values of I
CL
mode specification bit (FAST MODE)
CL
mode. When this bit is set to "0", Standard clock mode is selected. When the bit is
CL
status when an ACK clock
DA
goes to "L" at the ACK clock generation. When the bit is set to "1", ACK non-
DA
is held in the "H" status at the ACK clock generation. However,
DA
2
C0 clock control register other than the ACK bit (ACKBIT) during
page 257 of 402
16. MULTI-MASTER I
) is used to set theACK control, S
16
2
C system clock(V
is generated. When this bit is set to "0", ACK return
(Note 1)
to "H") and receives the ACK bit generated by the data receive
DA
2
C bus clock circuit is reset and the data can
2
C bus INTERFACE
mode and the S
CL
2
C0 clock control register and
).
IIC
CL
2
C bus