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18.4.7
IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred in synchronization with the internal
clock. Figures 18.18 to 18.20 show the IRIC set timing and SCL control.
When WAIT = 0, and FS = 0 or FSX = 0 (I
SCL
SDA
IRIC
User processing
SCL
SDA
IRIC
User processing
Figure 18.18 IRIC Setting Timing and SCL Control (1)
7
8
7
8
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
7
8
7
8
(b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception.
2
C bus format, no wait)
9
1
A
1
Clear IRIC
9
A
Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
Rev. 1.00 Apr. 28, 2008 Page 577 of 994
2
Section 18 I
C Bus Interface (IIC)
2
3
2
3
1
1
Clear IRIC
REJ09B0452-0100
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