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17.5.6
IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figures 17.13 to 17.15 show the IRIC flag timings and SCL control, and figure
17.16 shows an example of the interrupt flag timing of the operation reservation adapter.
When WAIT = 0 while FS = 0 or FSX = 0 (I
SCL
SDA
IRIC
User processing
(a) Data transfer ends with ICDRE = 0 for transmission or ICDRF = 0 for reception
SCL
SDA
IRIC
User processing
(b) Data transfer ends with ICDRE = 1 for transmission or ICDRF = 1 for reception
Figure 17.13 IRIC Flag Timing and SCL Control (1)
2
C bus format, no wait)
7
8
9
7
8
A
Clear IRIC
7
8
9
7
8
A
Clear IRIC
Section 17 I
1
2
3
1
2
3
1
1
Write to ICDR (transmit)
or read from ICDR (receive)
Rev. 3.00 Jan 25, 2006 page 527 of 872
2
C Bus Interface (IIC)
Clear IRIC
REJ09B0286-0300
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