Figure 10.39 Tgi Interrupt Timing (Input Capture); Figure 10.40 Tciv Interrupt Setting Timing - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer
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TGF Flag Setting Timing in Case of Input Capture: Figure 10.39 shows the timing for setting
of the TGF flag in TSR on input capture, and TGI interrupt request signal timing.
φ
Input capture
signal
TCNT
TGR
TGF flag
TGI interrupt

Figure 10.39 TGI Interrupt Timing (Input Capture)

TCFV Flag/TCFU Flag Setting Timing: Figure 10.40 shows the timing for setting of the TCFV
flag in TSR on overflow, and TCIV interrupt request signal timing.
Figure 10.41 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU
interrupt request signal timing.
φ
TCNT input
clock
TCNT
(overflow)
Overflow
signal
TCFV flag
TCIV interrupt
N
H'FFFF

Figure 10.40 TCIV Interrupt Setting Timing

Section 10 16-Bit Timer Pulse Unit (TPU)
N
H'0000
Rev. 6.00 Mar 15, 2006 page 231 of 570
REJ09B0211-0600

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