Dmac Timing - Renesas H8S/2633 Series Hardware Manual

25.3.4

DMAC Timing

Table 25-8 shows the DMAC timing.
Table 25-8 DMAC Timing
Condition A: V = PLLV
CC
V = 3.6 V to AV
ref
to +75°C (regular specifications), T
Condition B: V = PLLV
CC
V = 4.5 V to AV
ref
+75°C (regular specifications), T
Item
DREQ setup time
DREQ hold time
TEND delay time
DACK delay time1
DACK delay time2
Notes: *1 AV = 3.3 V to 5.5 V if A/D and D/A not used (pins used as I/O ports).
CC
*2 Vref = 3.3 V to AV
1034
= 3.0 V to 3.6 V, PV
CC
* 2
, V = AV
CC SS SS
= 3.0 V to 3.6 V, PV
CC
, V = AV = PLLV
CC SS SS
a
Condition A
Symbol Min
t 40
DRQS
t 10
DRQH
t —
TED
t —
DACD1
t —
DACD2
if A/D and D/A not used (pins used as I/O ports).
CC
= 3.0 V to 5.5 V, AV
CC
= PLLV = 0 V, ø = 2 to 16 MHz, T
SS
= –40°C to +85°C (wide-range specifications)
a
= 4.5 V to 5.5 V, AV
CC
= 0 V, ø = 2 to 25 MHz, T
SS
= –40°C to +85°C (wide-range specifications)
Condition B
Max Min Max
— 25 —
— 10 —
30 — 20
30 — 18
30 — 18
= 3.6 V to 5.5 V * 1
,
CC
= –20°C
a
= 4.5 V to 5.5 V,
CC
= –20°C to
a
Unit Test Conditions
ns Figure 25-19
Figure 25-18
ns Figure 25-16,
figure 25-17