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12.2.7
Port 1 Data Direction Register (P1DDR)
Bit
:
7
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value :
0
R/W
:
W
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1.
Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must
be set to 1. For further information about P1DDR, see sections 10A.2 and 10B.2, Port 1.
12.2.8
Module Stop Control Register A (MSTPCRA)
Bit
:
7
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
0
R/W
:
R/W
MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPA3 bit in MSTPCRA is set to 1, PPG operation stops at the end of the bus cycle
and a transition is made to module stop mode. Registers cannot be read or written to in module
stop mode. For details, see section 24.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset and in software standby mode.
Bit 3—Module Stop (MSTPA3): Specifies the PPG module stop mode.
Bit 3
MSTPA3
Description
0
PPG module stop mode cleared
1
PPG module stop mode set
616
6
5
0
0
W
W
6
5
0
1
R/W
R/W
R/W
4
3
2
0
0
0
W
W
W
4
3
2
1
1
1
R/W
R/W
1
0
0
0
W
W
1
0
1
1
R/W
R/W
(Initial value)
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