Port 1 Data Direction Register (P1Ddr); Port 2 Data Direction Register (P2Ddr) - Renesas H8S Series Hardware Manual

Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins
PO7 to PO4).
Bit 1
G1NOV
0
1
Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping operation for pulse output group 0 (pins
PO3 to PO0).
Bit 0
G0NOV
0
1
11.2.7

Port 1 Data Direction Register (P1DDR)

Bit : 7
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value : 0
R/W : W
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1.
Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must be set to 1. For further
information about P1DDR, see section 9.2, Port 1.
11.2.8

Port 2 Data Direction Register (P2DDR)

Bit : 7
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
Initial value : 0
R/W : W
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2.
Port 2 is multiplexed with pins PO7 to PO0. Bits corresponding to pins used for PPG output must be set to 1. For further
information about P2DDR, see section 9.3, Port 2.
Description
Normal operation in pulse output group 1 (output values updated at compare match A
in the selected TPU channel)
Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
Description
Normal operation in pulse output group 0 (output values updated at compare match A
in the selected TPU channel)
Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
6 5
0 0
W W
6 5
0 0
W W
4 3 2
0 0 0
W W W
4 3 2
0 0 0
W W W
(Initial value)
(Initial value)
1 0
0 0
W W
1 0
0 0
W W
Rev.6.00 Oct.28.2004 page 421 of 1016
REJ09B0138-0600H