Timer Output Master Enable Register (Toer) - Renesas F-ZTAT H8 Series Hardware Manual

10.2.5

Timer Output Master Enable Register (TOER)

TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3
and 4.
Bit 7
—
Initial value 1
Read/Write —
Reserved bits
TOER is initialized to H'FF by a reset and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bit 5—Master Enable TOCXB4 (EXB4): Enables or disables ITU output at pin TOCXB
Bit 5: EXB4 Description
0 TOCXB
a generic input/output pin).
If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in channel 1.
1 TOCXB
Bit 4—Master Enable TOCXA4 (EXA4): Enables or disables ITU output at pin TOCXA
Bit 4: EXA4 Description
0 TOCXA
a generic input/output pin).
If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1.
1 TOCXA
6 5 4
— EXB4 EXA4
1 1 1
— R/W R/W
Master enable TOCXA
These bits enable or disable output
settings for pins TOCXA
Master enable TIOCA
These bits enable or disable output settings for pins
TIOCA
3
output is disabled regardless of TFCR settings (TOCXB
4
is enabled for output according to TFCR settings
4
output is disabled regardless of TFCR settings (TOCXA
4
is enabled for output according to TFCR settings
4
Section 10 16-Bit Integrated Timer Unit (ITU)
3 2
EB3 EB4
1 1
R/W R/W
, TOCXB
4 4
and TOCXB
4 4
, TIOCB
3
, TIOCB , TIOCA , and TIOCB
3 4
Rev. 3.00 Mar 21, 2006 page 323 of 814
1 0
EA4 EA3
1 1
R/W R/W
, TIOCA , TIOCB
3 4 4
4
.
4
operates as
4
(Initial value)
.
4
operates as
4
(Initial value)
REJ09B0302-0300