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Bit
Bit Name
0
TOA
[Legend]
X:
Don't care
Note:
* The change of the setting is immediately reflected in the output value.
12.3.3
Timer Interrupt Enable Register W (TIERW)
TIERW controls the timer W interrupt request.
Bit
Bit Name
7
OVIE
6 to 4
3
IMIED
2
IMIEC
1
IMIEB
0
IMIEA
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Initial
Value
R/W
Description
0
R/W
Timer Output Level Setting A
Sets the output value of the FTIOA pin until the first
compare match A is generated.
0: Output value is 0*
1: Output value is 1*
Initial
Value
R/W
Description
0
R/W
Timer Overflow Interrupt Enable
When this bit is set to 1, FOVI interrupt requested by OVF
flag in TSRW is enabled.
All 1
Reserved
These bits are always read as 1.
0
R/W
Input Capture/Compare Match Interrupt Enable D
When this bit is set to 1, IMID interrupt requested by
IMFD flag in TSRW is enabled.
0
R/W
Input Capture/Compare Match Interrupt Enable C
When this bit is set to 1, IMIC interrupt requested by
IMFC flag in TSRW is enabled.
0
R/W
Input Capture/Compare Match Interrupt Enable B
When this bit is set to 1, IMIB interrupt requested by
IMFB flag in TSRW is enabled.
0
R/W
Input Capture/Compare Match Interrupt Enable A
When this bit is set to 1, IMIA interrupt requested by
IMFA flag in TSRW is enabled.
Rev. 1.00, 11/03, page 157 of 376
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