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Table 5.4
Clock Frequency and Settling Time (Times are in ms)
STS2
STS1
STS0
0
0
0
1
1
0
1
1
*
*
Legend: * Don't care
• When an External Clock is Used
Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set.
5.3.4
Transition to Standby Mode and Port Pin States
The system goes from active (high-speed or medium-speed) mode to standby mode when a
SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared
to 0, and bit TMA3 in TMA is cleared to 0. Port pins (except those with their MOS pull-up turned
on) enter high-impedance state when the transition to standby mode is made. This timing is shown
in figure 5.2.
φ
Internal
SLEEP instruction fetch
data bus
Port pins
Active (high-speed or medium-speed) mode
Figure 5.2 Transition to Standby Mode and Port Pin States
Waiting Time
5 MHz
8,192 states
1.6
16,384 states
3.2
32,768 states
6.6
65,536 states
13.1
131,072 states
26.2
Next instruction fetch
SLEEP instruction
execution
Output
5. Power-Down Modes
4 MHz
2 MHz
1 MHz
2.0
4.1
8.2
4.1
8.2
16.4
8.2
16.4
32.8
16.4
32.8
65.5
32.8
65.5
131.1
Internal
processing
High-impedance
Standby mode
Rev.3.00 Jul. 19, 2007 page 109 of 532
0.5 MHz
16.4
32.8
65.5
131.1
262.1
REJ09B0397-0300
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