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Table 5.4
Clock Frequency and Settling Time (Times are in ms)
STS2
STS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
• When an external clock is used
STS2 = 1, STS1 = 0, and STS0 = 1 are recommended. Other values can be set, but with other
settings, operation may start before the standby time is over.
5.3.4
Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is
cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the high-
impedance state (except pins for which the pull-up MOS is designated as on). Figure 5.2 shows
the timing in this case.
φ
Internal data bus
Pins
Active (high-speed) mode or active (medium-speed) mode
STS0
Waiting Time
0
8,192 states
1
16,384 states
0
32,768 states
1
65,536 states
0
131,072 states
1
2 states (not available)
0
8 states
1
16 states
SLEEP instruction fetch
SLEEP instruction execution
Port output
Figure 5.2 Standby Mode Transition and Pin States
Fetch of next instruction
Rev. 6.00 Aug 04, 2006 page 141 of 680
Section 5 Power-Down Modes
2 MHz
1 MHz
4.1
8.2
8.2
16.4
16.4
32.8
32.8
65.5
65.5
131.1
0.001
0.002
0.004
0.008
0.008
0.016
Internal processing
High-impedance
Standby mode
REJ09B0145-0600
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