Table of Contents
Advertisement
Section 8 DMA Controller
8.4.14
DMAC States in Reset State, Standby Modes, and Sleep Mode
When the chip is reset or enters hardware or software standby mode, the DMAC is initialized and
halts. DMAC operations continue in sleep mode. Figure 8.24 shows the timing of a cycle-steal
transfer in sleep mode.
CPU cycle
T
2
φ
Address bus
RD
HWR LWR
,
Figure 8.24 Timing of Cycle-Steal Transfer in Sleep Mode
Rev. 3.00 Mar 21, 2006 page 238 of 814
REJ09B0302-0300
DMAC cycle
T
T
T
T
T
d
1
2
1
2
Sleep mode
DMAC cycle
T
T
T
T
d
1
2
1
T
T
2
d
Advertisement
Table of Contents
