Repeat Mode - Renesas F-ZTAT H8 Series Hardware Manual

16-bit single-chip microcomputer

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Section 8 DMA Controller

Repeat Mode

Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable

timing pattern controller (TPC) in synchronization, for example, with ITU compare match. Repeat

mode can be selected for each channel independently.

One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number

of these transfers are executed. One address is specified in the memory address register (MAR),

the other in the I/O address register (IOAR). At the end of the designated number of transfers,

MAR and ETCR are restored to their original values and operation continues. The direction of

transfer is determined automatically from the activation source. The transfer is from the address

specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-data-

full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise.

Table 8.8 indicates the register functions in repeat mode.

Rev. 7.00 Sep 21, 2005 page 225 of 878

REJ09B0259-0700

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