Repeat Mode - Renesas H8S/2633 Series Hardware Manual

8.5.4

Repeat Mode

Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to
0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer
request, and this is executed the number of times specified in ETCR. On completion of the
specified number of transfers, MAR and ETCRL are automatically restored to their original
settings and operation continues.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 8-8 summarizes register functions in repeat mode.
Table 8-8 Register Functions in Repeat Mode
Register
23
MAR
23 15
H'FF
IOAR
7
ETCRH
7
Legend
MAR : Memory address register
IOAR : I/O address register
ETCR : Transfer count register
DTDIR : Data transfer direction bit
282
Function
DTDIR = 0 DTDIR = 1 Initial Setting
0 Source
address
register
0
Destination
address
register
0
Holds number of
transfers
Transfer counter
0
ETCRL
Destination Start address of
address transfer destination
register or transfer source
Source Start address of
address transfer source or
register transfer destination
Number of transfers
Number of transfers
Operation
Incremented/
decremented every
transfer. Initial
setting is restored
when value reaches
H'0000
Fixed
Fixed
Decremented every
transfer. Loaded with
ETCRH value when
count reaches H'00