Dma Control Register (Dctrl_0_7, Dctrl_8_15) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.4.14

DMA Control Register (DCTRL_0_7, DCTRL_8_15)

This register sets the transfer type for descriptor access and the arbitration between channels.
(DCTRL_0_7 is common for channels 0 to 7 and DCTRL_8_15 is common for channels 8 to 15.)
Bit:
31
Initial value:
0
R/W:
R/W
Bit:
15
-
0
Initial value:
R/W:
R
Initial
Bit Bit Name Value
31 to 28 LWCA 0000
27 — 0
26 to 24 LWPR 000
23 to 20 LDCA 0000
19 — 0
18 to 16 LDPR 000
15 to 2 — All 0
1 LVINT 0
0 PR 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
LWCA -
0 0 0 0 0
R/W R/W R/W R R/W
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
R/W Description
R/W Link WriteBack CACHE
Sets the value to be output to AWCACHE[3:0] during descriptor writeback in link mode.
For the setting value, see Note in section 9.4.11, Channel Extension Register n
(CHEXT_n).
R Reserved area. Set 0. The initial value is 0.
R/W Link WriteBack PROT
Sets the value to be output to AWPROT[2:0] during descriptor writeback in link mode.
For the setting value, see AMBA AXI Protocol Specification from Arm Limited.
R/W Link Descriptor CACHE
Sets the value to be output to ARCACHE[3:0] during descriptor load in link mode. For the
setting value, see Note in section 9.4.11, Channel Extension Register n (CHEXT_n).
R Reserved area. Set 0. The initial value is 0.
R/W Link Descriptor PROT
Sets the value to be output to ARPROT[2:0] during descriptor load in link mode.
For the setting value, see AMBA AXI Protocol Specification from Arm Limited.
R Reserved area. Set 0. A read operation results in 0 being read.
R/W Sets whether to use pulse output or level output for the DMA transfer end interrupt and
DMA error interrupt. Set pulse output for this product.
0: Pulse output (initial value)
1: Level output
R/W Sets the transfer priority control mode between channels (see section 9.7.2, Priority
Control for DMA Channels.
0: Fixed priority mode (initial value)
1: Round robin mode
25 24 23 22 21
LWPR LDCA
0 0 0 0 0
R/W R/W R/W R/W R/W
9 8 7 6 5
- - - - -
0 0 0 0 0
R R R R R
9. Direct Memory Access Controller
20 19 18 17 16
- LDPR
0 0 0 0 0
R/W R R/W R/W R/W
4 3 2 1 0
- - - LVINT PR
0 0 0 0 0
R R R R/W R/W
9-25