Section 7 Dma Controller; Overview; Features - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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The H8S/2357 Group has a on-chip DMA controller (DMAC) which can carry out data transfer on up to 4 channels.

The features of the DMAC are listed below.

• Choice of short address mode or full address mode

Short address mode

 Maximum of 4 channels can be used

 Choice of dual address mode or single address mode

 In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and

the other as 16 bits

 In single address mode, transfer source or transfer destination address only is specified as 24 bits

 In single address mode, transfer can be performed in one bus cycle

 Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode

Full address mode

 Maximum of 2 channels can be used

 Transfer source and transfer destination address specified as 24 bits

 Choice of normal mode or block transfer mode

• 16-Mbyte address space can be specified directly

• Byte or word can be set as the transfer unit

• Activation sources: internal interrupt, external request, auto-request (depending on transfer mode)

 Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts

 Serial communication interface (SCI0, SCI1) transmission data empty interrupt, reception data full interrupt

 A/D converter conversion end interrupt

 External request

 Auto-request

• Module stop mode can be set

 The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode

Section 7 DMA Controller

Rev.6.00 Oct.28.2004 page 165 of 1016

REJ09B0138-0600H