Section 7 Dma Controller (Dmac); Features - Renesas H8SX/1500 Series Hardware Manual

Section 7 DMA Controller (DMAC)

This LSI includes a 4-channel DMA controller (DMAC).
7.1

Features

• Maximum of 4-G byte address space can be accessed
• Byte, word, or longword can be set as data transfer unit
• Maximum of 4-G bytes (4,294,967,295 bytes) can be set as total transfer size
Supports free-running mode in which total transfer size setting is not needed
• DMAC activation methods are auto-request, on-chip module interrupt, and external request.
Auto request: CPU activates (cycle stealing or burst access can be selected)
On-chip module interrupt: Interrupt requests from on-chip peripheral modules can be selected
External request*: Low level or falling edge detection of the DREQ signal can be selected
• Dual or single address mode can be selected as address mode
Dual address mode: Both source and destination are specified by addresses
Single address mode*: Either source or destination is specified by the DREQ signal and the
other is specified by address
• Normal, repeat, or block transfer can be selected as transfer mode
Normal transfer mode: One byte, one word, or one longword data is transferred at a single
Repeat transfer mode:
Block transfer mode:
• Extended repeat area function which repeats the addressees within a specified area using the
transfer address with the fixed upper bits (ring buffer transfer can be performed, as an
example) is available
One bit (two bytes) to 27 bits (128 Mbytes) for transfer source and destination can be set as
extended repeat areas
as an activation source
(external request is available for all four channels)
transfer request
One byte, one word, or one longword data is transferred at a single
transfer request
Repeat size of data is transferred and then a transfer address returns to
the transfer start address
Up to 65536 transfers (65,536 bytes/words/longwords) can be set as
repeat size
One block data is transferred at a single transfer request
Up to 65,536 bytes/words/longwords can be set as block size
Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar. 14, 2006 Page 133 of 804
REJ09B0104-0300