Figure 25.17 Basic Bus Timing For Normal Space (One Cycle Of Software Wait, External Wait Cycle Valid (Wm Bit = 0), No Idle Cycle) - Renesas HD6417641 Hardware Manual

CKIO
A25 to A0
CSn
RD/WR
RD
Read
D15 to D0
WEn
Write
D15 to D0
BS
t
DACKn*
WAIT
Note: * Waveform for DACKn when active low is selected.
Figure 25.17 Basic Bus Timing for Normal Space
(One Cycle of Software Wait, External Wait Cycle Valid (WM Bit = 0), No Idle Cycle)
T1 Tw
t
AD1
t
AS
t
CSD1
t
RWD1
t t
RSD RSD
t t
WED1 WED1
t
WDD1
t t
BSD BSD
DACD
t
WTH1
t
WTS1
Section 25 Electrical Characteristics
T2 Taw T1
t t
AD1 AD1
tAS
t t
CSD1 CSD1
t t
RWD1 RWD1
t t
AH RSD
t
RDH1
t
RDS1
t
t
WED1
AH
t t
WDH1 WDD1
t
BSD
t t
DACD DACD
t
Rev. 4.00 Sep. 14, 2005 Page 929 of 982
Tw T2 Taw
t
AD1
t
CSD1
t
RWD1
t t
RSD AH
t
RDH1
t
RDS1
t t
WED1 AH
t
WDH1
t
BSD
t
DACD
WTH1
t
WTS1
REJ09B0023-0400