Refresh Control Register (Refcr) - Renesas H8S/2368 Series Hardware Manual

6.3.10

Refresh Control Register (REFCR)

REFCR specifies DRAM interface refresh control.
Note: The DRAM interface is not supported by the H8S/2366.
Bit Bit Name
15 CMF
14 CMIE
13 RCW1
12 RCW0
−
11
Note: * Only 0 can be written, to clear the flag.
Initial Value R/W
0 R/(W)*
0 R/W
0 R/W
0 R/W
0 R/W
Description
Compare Match Flag
Status flag that indicates a match between the
values of RTCNT and RTCOR.
[Clearing conditions]
•
When 0 is written to CMF after reading CMF
= 1 while the RFSHE bit is cleared to 0
•
When CBR refreshing is executed while the
RFSHE bit is set to 1
[Setting condition]
When RTCOR = RTCNT
Compare Match Interrupt Enable
Enables or disables interrupt requests (CMI) by
the CMF flag when the CMF flag is set to 1.
This bit is valid when refresh control is not
performed. When the refresh control is
performed, this bit is always cleared to 0 and
cannot be modified.
0: Interrupt request by CMF flag disabled
1: Interrupt request by CMF flag enabled
CAS-RAS Wait Control
These bits select the number of wait cycles to
be inserted between the CAS assert cycle and
RAS assert cycle in a DRAM refresh cycle.
00: Wait state not inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
Rev. 2.00, 05/03, page 129 of 820