Dtc Activation By Interrupt; Usage Notes; Contention Between Interrupt Generation And Disabling; Table 5.5 Number Of States In Interrupt Handling Routine Execution Status - Renesas H8S Series Hardware Manual

Section 5 Interrupt Controller
Table 5.5 Number of States in Interrupt Handling Routine Execution Status
Symbol
Instruction fetch
Branch address read
Stack manipulation
Legend:
M: Number of wait states in an external device access.
Note: * Cannot be used in this LSI.
5.6.5

DTC Activation by Interrupt

The DTC can be activated by an interrupt. For details, see section 8, Data Transfer Controller
(DTC).
Note: No DTC is implemented in the H8S/2614 and H8S/2616.
5.7

Usage Notes

5.7.1

Contention between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5.6 shows an example in which the TGIEA bit in the TPU's TIER_0 register is cleared to 0.
Rev. 6.00 Mar 15, 2006 page 86 of 570
REJ09B0211-0600
Internal 2-State
Memory Access
S 1 4
I
S
J
S
K
Object of Access
External Device *
8 Bit Bus
3-State 2-State
Access Access
6 + 2m 2
16 Bit Bus
3-State
Access
3 + m