Dtc And Dmac* Activation By Interrupt; Usage Notes; Contention Between Interrupt Generation And Disabling - Renesas H8S/2368 Series Hardware Manual

5.6.5

DTC and DMAC* Activation by Interrupt

The DTC and DMAC* can be activated by an interrupt. In this case, the following options are
available:
• Interrupt request to CPU
• Activation request to DTC
• Activation request to DMAC*
• Selection of a number of the above
For details of interrupt requests that can be used to activate the DTC and DMAC*, see table 5.2
and section 8, Data Transfer Controller (DTC) and section 7, DMA Controller (DMAC)*.
Note: * Not supported by the H8S/2366.
5.7

Usage Notes

5.7.1

Contention between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt
source flag is cleared to 0. Figure 5.6 shows an example in which the TCIEV bit in the TPU's
TIER_0 register is cleared to 0. The above contention will not occur if an enable bit or interrupt
source flag is cleared to 0 while the interrupt is masked.
Rev. 2.00, 05/03, page 103 of 820