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10.3.5
SHI Slave Address Register (HSAR)—DSP Side
The 24-bit slave address register (HSAR) is used when the SHI operates in the I
register is ignored in the other operational modes. The HSAR register holds 5 bits of the 7-bit slave device
address. The SHI also acknowledges the general call address specified by the I
comprising a 7-bit address and a R/W bit), but treats any following data bytes as regular data. That is, the
SHI does not differentiate between its dedicated address and the general call address. Note that the host
processor cannot access the HSAR register.
10.3.5.1
HSAR Reserved Bits—Bits 19, 17–0
These bits are reserved; they read as zero and should be written with zeroes for future compatibility.
2
10.3.6
HSAR I
2
Part of the I
C slave device address is stored in the read/write HA[6:3] and HA1 bits of the HSAR register.
The full 7-bit slave device address is formed by combining the HA[6:3] and HA1 bits with the HA0 and
HA2 pins, to obtain the HA[6:0] slave device address. Whenever an I
transfer, the full 7-bit slave device address is compared to the received address byte. During hardware or
software resets, HA[6:3] = 1011 and the HA1 bit is cleared; this results in a default slave device address
of 1011[HA2]0[HA0].
10.3.7
SHI Clock Control Register (HCKR)—DSP Side
The HCKR register is a 24-bit read/write register that controls the SHI clock generator. The HCKR bits
should be changed only while the SHI is in the individual reset state (HEN = 0 in the HCSR register).
For proper SHI clock set-up, please consult the data sheet. The programmer should not use the
combination HRS = 1 and HDM[7:0] = 00000000, since that combination may cause synchronization
problems and improper operations (it is an illegal combination).
The HCKR bits are cleared during hardware or software resets, except for CPHA, which is set. The HCKR
register is not affected by the stop state. The HCKR bits are described in the following sections.
10.3.7.1
Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0
The Clock Phase (CPHA) bit controls the relationship between the data on the master-in-slave-out (MISO)
pin and master-out-slave-in (MOSI) pin, and also the clock produced or received at the SCK pin. The
CPOL bit determines the clock polarity (1 = active-high clock, 0 = active-low clock).
The clock phase and polarity should be identical for both the master and slave SPI devices. The CPHA and
CPOL bits are functional only when the SHI operates in the SPI mode; the CPHA and CPOL bits are
2
ignored in the I
C mode. During hardware and software resets, the CPHA bit is set and the CPOL bit is
cleared.
When operating in the SPI mode, you can select any one of four combinations of serial clock (SCK) phase
and polarity. (See
Figure
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
C Slave Address (HA[6:3], HA1)—Bits 23–20,18
10-6.)
Serial Host Interface (SHI, SHI_1)
2
C slave mode; the HSAR
2
C protocol (8 zeroes
2
C master device initiates an I
2
C bus
10-7
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