Itu Output Timing - Renesas F-ZTAT H8 Series Hardware Manual

Section 10 16-Bit Integrated Timer Unit (ITU)
10.4.9

ITU Output Timing

The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external
trigger, or inverted by bit settings in TOCR.
Timing of Enabling and Disabling of ITU Output by TOER: In this example an ITU output is
disabled by clearing a master enable bit to 0 in TOER. An arbitrary value can be output by
appropriate settings of the data register (DR) and data direction register (DDR) of the
corresponding input/output port. Figure 10.54 illustrates the timing of the enabling and disabling
of ITU output by TOER.
φ
Address bus
TOER
ITU output pin
Figure 10.54 Timing of Disabling of ITU Output by Writing to TOER (Example)
Rev. 3.00 Mar 21, 2006 page 376 of 814
REJ09B0302-0300
T T
1 2
TOER address
Timer output
ITU output
T
3
I/O port
Generic input/output