Usage Notes; Module Stop Mode Setting; Input Clock Restrictions; Figure 9.45 Timing For Status Flag Clearing By Dmac Activation (2) - Renesas H8SX/1500 Series Hardware Manual

Pφ
Address
Period in which the next transfer request is masked
Status flag
Interrupt request
signal

Figure 9.45 Timing for Status Flag Clearing by DMAC Activation (2)

9.9

Usage Notes

9.9.1

Module Stop Mode Setting

Operation of the TPU can be disabled or enabled using the module stop control register. The initial
setting is for operation of the TPU to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 19, Power-Down Modes.
9.9.2

Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.46 shows the input clock
conditions in phase counting mode.
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Note: Phase difference, Overlap ≥ 1.5 states

Figure 9.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

Source address
Phase
Overlap difference difference
Overlap
Pulse width
Pulse width ≥ 2.5 states
Section 9 16-Bit Timer Pulse Unit (TPU)
DMAC
read cycle
Period of flag clearing
Period of interrupt request signal clearing
Phase
Pulse width
Pulse width
Rev. 3.00 Mar. 14, 2006 Page 337 of 804
DMAC
write cycle
Destination address
Pulse width
REJ09B0104-0300