Usage Notes; Module Stop Mode Setting; Input Clock Restrictions; Caution On Period Setting - Renesas H8S Series Hardware Manual

Section 10 16-Bit Timer Pulse Unit (TPU)
10.9

Usage Notes

10.9.1

Module Stop Mode Setting

TPU operation can be disabled or enabled using the module stop control register. The initial
setting is for TPU operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 20, Power-Down Modes.
10.9.2

Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.44 shows the input clock
conditions in phase counting mode.
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Notes: Phase difference and overlap
Pulse width

Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

10.9.3

Caution on Period Setting

When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
φ
f =
(N + 1)
Rev. 6.00 Mar 15, 2006 page 234 of 570
REJ09B0211-0600
Phase Phase
differ- differ-
Overlap Overlap
ence ence
Pulse width
: 1.5 states or more
: 2.5 states or more
Pulse width
Pulse width
Pulse width