Phase Counting Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.4.6

Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/
decremented accordingly. This mode can be set for channels 1 and 2.
When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/
down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the
functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match
and interrupt functions can be used.
This can be used for two-phase encoder pulse input.
If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting
down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down.
Table 10.45 shows the correspondence between external clock pins and channels.
Table 10.45 Phase Counting Mode Clock Input Pins
Channels
When channel 1 is set to phase counting mode
When channel 2 is set to phase counting mode
(1) Example of Phase Counting Mode Setting Procedure
Figure 10.29 shows an example of the phase counting mode setting procedure.
Figure 10.29 Example of Phase Counting Mode Setting Procedure
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Phase counting mode
Select phase counting
[1]
mode
[2]
Start count
<Phase counting mode>
10. Multi-Function Timer Pulse Unit 2
External Clock Pins
A-Phase
TCLKA
TCLKC
[1] Select phase counting mode with bits
MD3 to MD0 in TMDR.
[2] Set the CST bit in TSTR to 1 to start
the count operation.
B-Phase
TCLKB
TCLKD
10-82