Cpu Interface; 16-Bit Accessible Registers - Renesas F-ZTAT H8 Series Hardware Manual

10.3

CPU Interface

10.3.1

16-Bit Accessible Registers

The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A
and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data
bus. These registers can be written or read a word at a time, or a byte at a time.
Figures 10.6 and 10.7 show examples of word access to a timer counter (TCNT). Figures 10.8 to
10.11 show examples of byte access to TCNTH and TCNTL.
On-chip data bus
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CPU L
Figure 10.6 Access to Timer Counter (CPU Writes to TCNT, Word)
On-chip data bus
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CPU L
Figure 10.7 Access to Timer Counter (CPU Reads TCNT, Word)
Bus interface
Bus interface
Section 10 16-Bit Integrated Timer Unit (ITU)
TCNTH TCNTL
TCNTH TCNTL
Rev. 7.00 Sep 21, 2005 page 349 of 878
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Module
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data bus
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Module
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data bus
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