Cpu Interface - Renesas H8 Series Hardware Manual

8-bit single-chip microcomputer

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Bit 1    Output Level A (OLVLA): Bit 1 selects the output level that is output at pin FTOA by

compare match A (when FRC matches OCRA).

Bit 1: OLVLA

Bit 0    Output Level B (OLVLB): Bit 0 selects the output level that is output at pin FTOB by

compare match B (when FRC matches OCRB).

Bit 0: OLVLB

CPU Interface

FRC, OCRA, OCRB, and ICRA to ICRD are 16-bit registers, but the CPU is connected to the on-

chip peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore

uses an 8-bit temporary register (TEMP).

These registers should always be accessed 16 bits at a time. If two consecutive byte-size MOV

instructions are used, the upper byte must be accessed first and the lower byte second. Data will

not be transferred correctly if only the upper byte or only the lower byte is accessed.

Rev. 6.00 Sep 12, 2006 page 253 of 526

Section 9 Timers

(initial value)

REJ09B0326-0600