Cpu; Features - Renesas RZ/A Series User Manual

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Table of Contents

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

CPU

This product incorporates the Arm single-core Cortex-A9 MPCore, where the IP version is r3p0.

• Instruction cache size: 32 Kbytes

• Data cache size

• TLB entries: 128 entries

• Jazelle architecture extension: Full

• Media processing engine with NEON technology: Included

• FPU: Included

• PTM interface: Included

• Wrappers to support for power off and dormant mode: Not included

• Preload engine: Not included

• Number of interrupts: 0 (On-chip interrupt controller is not used.)

• Accelerator Coherence Port: Not included

For details, refer to Cortex-A9 MPCore Technical Reference Manual issued by Arm Ltd.

Contents of memory regions which are set as write-through are not cached even if data caching is enabled.

For details, refer to Cortex-A9 Technical Reference Manual issued by Arm Ltd.

R01UH0437EJ0600 Rev.6.00

Jan 29, 2021

Rz/a1 series Rz/a1lu series Rz/a1lc series