Bus Cycle When Transfer Is Aborted - Renesas F-ZTAT H8 Series Hardware Manual

8.6.8

Bus Cycle when Transfer is Aborted

When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME
bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead
cycle may occur. This dead cycle does not update the halted channel's address register or counter
value. Figure 8.27 shows an example in which an auto-requested transfer in cycle-steal mode on
channel 0 is aborted by clearing the DTE bit in channel 0.
CPU cycle
T
1
φ
Address bus
RD
HWR, LWR
Figure 8.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode
DMAC cycle
T T T T
2 d 1 2
CPU cycle
T T T T
1 2 1 2
DTE bit is
cleared
Rev. 7.00 Sep 21, 2005 page 255 of 878
Section 8 DMA Controller
DMAC
cycle CPU cycle
T T T T T
3 d d 1
REJ09B0259-0700
2