Number Of States Of An External Bus Cycle; Dma Transfer Request - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.7.3

Number of States of an External Bus Cycle

When this module is the bus master, the number of states of an external bus cycle is controlled by the bus state controller
as when the CPU is the bus master. For details, refer to section 8, Bus State Controller.
9.7.4

DMA Transfer Request

Edge detection or level detection can be selected using the LVL bit of the CHCFG_n register.
The HIEN and LOEN bits of the CHCFG_n register are used to select either the rising edge or falling edge in the case of
edge detection or either the high level or low level in the case of level detection.
When the transfer request is by an on-chip peripheral module, set the CHCFG_n register according to Table 9.4, On-
Chip Peripheral Module Requests.
When the transfer request is by the external pin (DREQ0), set the detection conditions (rising/falling edge and high/low
level) according to Table 9.18, Setting for Detection of External Pin Request.
Table 9.18 Setting for Detection of External Pin Request
LVL
Mode (CHCFG_0)
Edge 0
detection
Level 1
detection
(1) Edge Detection
Setting 0 in the LVL bit of the CHCFG_n register enables edge detection.
When 1 is set in the HIEN bit of the CHCFG_n register, rising edge detection is enabled. When 1 is set in the LOEN bit,
falling edge detection is enabled.
Wait for DACK0 to be detected, before issuing the next DREQ0 request.
CKIO
DREQ0
Internal request
DACK0
DMA Transfer
Figure 9.15 Edge Detection Timing (HIEN = 1, REQD = 0)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
HIEN LOEN
(CHCFG_0) (CHCFG_0)
0 0
1
1 0
1
0 0
1
1 0
1
Read
9. Direct Memory Access Controller
Function
Specify this value when you use auto request triggers.
Detects external pin request (DREQ0) at its falling edge.
Detects external pin request (DREQ0) at its rising edge.
Setting prohibited
Setting prohibited
Detects external pin request (DREQ0) in Low level mode.
Detects external pin request (DREQ0) in High level mode.
Setting prohibited
Write Read
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