Table of Contents
Advertisement
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt
requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when
PSRAME = 1 or DRAME = 1.
Bit 6: CMIE
Description
0
The CMI interrupt requested by CMF is disabled
1
The CMI interrupt requested by CMF is enabled
Bits 5 to 3—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source for
input to RTCNT. When used for refresh control, the refresh controller outputs a refresh request at
periodic intervals determined by compare match between RTCNT and RTCOR. When used as an
interval timer, the refresh controller generates CMI interrupts at periodic intervals determined by
compare match. These bits are write-disabled when the PSRAME bit or DRAME bit is set to 1.
Bit 5: CKS2
Bit 4: CKS1
0
0
1
1
0
1
Bits 2 to 0—Reserved: Read-only bits, always read as 1.
7.2.3
Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit readable/writable up-counter.
Bit
7
Initial value
0
Read/Write
R/W
RTCNT is an up-counter that is incremented by an internal clock selected by bits CKS2 to CKS0
in RTMCSR. When RTCNT matches RTCOR (compare match), the CMF flag is set to 1 and
RTCNT is cleared to H'00.
Bit 3: CKS0
0
1
0
1
0
1
0
1
6
5
4
0
0
0
R/W
R/W
R/W
Section 7 Refresh Controller
Description
Clock input is disabled
φ/2 clock source
φ/8 clock source
φ/32 clock source
φ/128 clock source
φ/512 clock source
φ/2048 clock source
φ/4096 clock source
3
2
0
0
R/W
R/W
R/W
Rev. 3.00 Mar 21, 2006 page 153 of 814
(Initial value)
(Initial value)
1
0
0
0
R/W
REJ09B0302-0300
Advertisement
Table of Contents
