Register Descriptions; Bus Control Register 2 (Bcr2) - Renesas H8SX/1520 Series Hardware Manual

Section 6 Bus Controller (BSC)
6.2

Register Descriptions

The bus controller has the following registers.

• Bus control register 2 (BCR2)

6.2.1 Bus Control Register 2 (BCR2)
BCR2 is used for bus arbitration control of the CPU and DMAC, and enabling/disabling of the
write data buffer function to the peripheral device.
Bit
Bit Name
Initial Value
R/W
Bit Bit Name

7, 6

5
4 IBCCS

3, 2

1
0 PWDBE
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7 6 5
— — —
0 0 0
R R R/W
Initial
Value R/W
All 0 R
0 R/W
0 R/W
All 0 R
1 R/W
0 R/W
4 3
IBCCS —
0 0
R/W R
Description
Reserved
These are read-only bits and cannot be modified.
Reserved
This bit is always read as 0. The write value should
always be 0.
Internal Bus Cycle Control Select
Selects the internal bus arbiter function.
0: Releases the bus mastership according to the priority
1: Executes the bus cycles alternatively when a CPU
bus mastership request conflicts with a DMAC bus
mastership request
Reserved
These are read-only bits and cannot be modified.
Reserved
This bit is always read as 1. The write value should
always be 1.
Peripheral Module Write Data Buffer Enable
Specifies whether or not to use the write data buffer
function for the peripheral module write cycles.
0: Write data buffer function not used
1: Write data buffer function used
2 1 0
— — PWDBE
0 1 0
R R/W R/W