Noise Canceller; Figure 13.28 Block Diagram Of Noise Canceler - Renesas H8S/2111B Hardware Manual

13.4.8

Noise Canceller

The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched
internally. Figure 13.28 shows a block diagram of the noise canceller.
The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
SCL or
SDA input signal
Sampling
clock
Rev. 1.00, 05/04, page 334 of 544
Sampling clock
C
D Q
Latch
System clock
cycle

Figure 13.28 Block Diagram of Noise Canceler

C
D Q
Latch
Internal SCL or
Match
SDA signal
detector