Table Of Instructions Classified By Function; Table 2.3 Operation Notation - Renesas H8SX/1520 Series Hardware Manual

Section 2 CPU
2.7.2

Table of Instructions Classified by Function

Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in
these tables is defined in table 2.3.
Table 2.3 Operation Notation
Operation Notation
Rd
Rs
Rn
ERn
(EAd)
(EAs)
EXR
CCR
VBR
SBR
N
Z
V
C
PC
SP
#IMM
disp
+
−
×
÷
∧
∨
⊕
→
∼
:8/:16/:24/:32
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Rev. 3.00 Mar. 14, 2006 Page 42 of 804
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Description
General register (destination)*
General register (source)*
General register*
General register (32-bit register)
Destination operand
Source operand
Extended control register
Condition-code register
Vector base register
Short address base register
N (negative) flag in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Program counter
Stack pointer
Immediate data
Displacement
Addition
Subtraction
Multiplication
Division
Logical AND
Logical OR
Logical exclusive OR
Move
Logical not (logical complement)
8-, 16-, 24-, or 32-bit length